Job Information
Nvidia Senior ASIC Physical Design and Timing Engineer in Santa Clara, California
We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing!
More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
What you'll be doing:
Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and SoCs at block level, cluster level, and/or full chip level.
Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
Work in a cross-functional environment interacting with multiple teams.
Apply knowledge and experience to improve the convergence flows working with the Methodology Team.
What we need to see:
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 2+ years experience in Synthesis and Timing
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.
Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
Background in logic synthesis and equivalence checking/FV required.
Expertise and in-depth knowledge of industry standard EDA tools.
Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc.
Ways to stand out from the crowd:
Background in high-performance designs, such as CPUs, GPUs or Network processor implementation and timing convergence, is a plus
Good understanding of hardware architecture and skills in RTL/logic design for timing closure, specifically experience in critical timing path planning and crafting.
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.
Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations.
Knowledge in circuits, SPICE simulations, and/or transistor level STA as well as Experience in methodology and/or flow development/automation.
The base salary range is 128,000 USD - 258,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
NVIDIA is a Learning Machine
NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and the metaverse is transforming the world's largest industries and profoundly impacting society.
Learn more about NVIDIA .